A 39x48 GENERAL-PURPOSE FOCAL-PLANE PROCESSOR ARRAY INTEGRATED CIRCUIT

This paper presents the implementation of a generalpurpose programmable vision chip, with a 39×48 SIMD processor-per-pixel array, fabricated in a 0.35μm CMOS technology. The chip employs Analogue Processing Elements to achieve cell density of 410 cells/mm. The array operates at 1.25MHz with power consumption of 12μW/cell and executes low-level image-processing algorithms in real-time. Chip architecture, circuit and layout design issues are discussed. Experimental results are presented.